Cadence Design’s price movement
Cadence Design Systems (CDNS) has a market capitalization of $6.2 billion. Cadence’s YTD (year-to-date) price movement has been rising quarter-over-quarter in 2015 and has created a pattern of double top between August and October 2015.
After its 3Q15 earnings report, Cadence fell by 0.23% to close at $21.35 per share as of October 26, 2015. Its price movements on a weekly, monthly, and YTD basis are 0.66%, 1.9%, and 12.6%, respectively.
Cadence has sometimes broken the support of its 20-day, 50-day, and 200-day moving averages in 2015. Currently, it’s trading at 0.87% above its 20-day moving average, 2.5% above its 50-day moving average, and 9.3% above its 200-day moving average.
The PowerShares DWA Technology Momentum ETF (PTF) invests 2.6% of its holdings in Cadence. The ETF tracks an index of US technology companies selected and weighted by price momentum. The ETF’s YTD price movement was 7.5% as of October 23, 2015.
Cadence Design Systems’ competitors and their market capitalizations are:
Performance of Cadence Design in 3Q15
The company reported net revenue of $433.8 million in 3Q15, a rise of 4.3% when compared to net revenue of $415.9 million in 2Q15. Its revenue from products and maintenance services rose by 3.1% and 19.3%, respectively, in 3Q15. Its net income and EPS (earnings per share) rose to $77.6 million and $0.25 per share in 3Q15, increases of 33.5% and 31.6%, respectively, on a quarterly basis.
Its cash and cash equivalents and inventories fell by 4.9% and 7.2%, respectively, on a quarterly basis in 3Q15. Its current ratio rose to 2.0 and its long-term debt-to-equity ratio fell to 0.31 in 3Q15 compared to 2.02 and 0.32, respectively, in 2Q15.
Below are some of Cadence’s key activities in 3Q15:
- Realtek Semiconductor utilized Cadence’s Palladium XP platform to accelerate the successful development and verification of a system-on-chip (or SoC) design.
- Altair Semiconductor adopted the Cadence Palladium XP platform for the verification and validation of its Internet of Things (IoT) SoC designs.
- The new Cadence Joules RTL Power Solution delivered 20x faster time-based RTL power analysis with a 15% accuracy.
- Cadence Design Systems, Mentor Graphics (MENT), and Breker Verification Systems collaborated on a technology contribution to the Accellera Portable Stimulus Working Group.
- The company announced a broad intellectual property (or IP) portfolio for TSMC’s (Taiwan Semiconductor Manufacturing Company) 10nm FinFET N10 process.
- Cadence’s digital, custom/analog, and signoff tools achieved certification from TSMC for V0.9 of its 10nm process and are looking forward to complete V1.0 by 4Q15.
- Cadence’s Innovus Implementation System achieved V0.9 certification for TSMC’s 10nm FinFET process and is looking forward to complete V1.0 in 4Q15.
About Cadence Design
Cadence provides EDA (electronic design automation) and semiconductor IP. Its custom/analog tools help engineers to design the transistors, standard cells, and IP blocks that make up SoCs. Its digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semiconductor processing nodes.