3D NAND is expected to be a significant part of trade NAND in 2016
In fiscal 3Q15, NAND accounted for 31% of Micron’s (MU) revenues. As we have seen in the prior part of this series, Micron is still keen on its 16-nm planar NAND technology owing to its cost efficiency.
However, now the question arises: If 16-nm planar NAND is that efficient, why is Micron aiming for 3D NAND? The answer lies in the flash memory’s manufacturing cost, which is directly proportional to its die size. Manufacturers always seek to shrink their fabrication process, as it allows more transistors to be packed into the same die area, thus increasing chip density at essentially no extra cost.
3D NAND’s higher density improves performance and reliability
3D NAND’s vertical stacking enables a significantly higher density of memory cells, and thus improves performance and reliability. 3D NAND overcomes the density limit associated within the planar (or 2D) NAND architecture. For comparison purposes, 3D NAND has a dense chip with two times the write performance and ten times the reliability of planar NAND. Thus, 3D NAND cell architecture allows for significant performance and cost improvement in comparison to planar technology. Thus, Micron aims to transition from 16-nm to 3D NAND in the near future.
The above chart shows the NAND die size of various players. The lower the die size, the better it is. Intel (INTC)-Micron’s NAND die is larger than that of its peers Samsung, Toshiba, and SanDisk (SNDK). However, die capacity alone cannot dictate Intel’s 3D NAND cost efficiency in comparison to Samsung’s (SSNLF), as they both have 32 layers. Intel has not disclosed the specifications, but currently the smallest pitch for single-patterning is between 30-nm and 40-nm. Micron’s strategic move towards 3D NAND is aimed at getting away from multi-patterning as a means to attain cost control.