31 May

INTC Adjusts Technology Road Map to Incorporate Node Optimization

WRITTEN BY Puja Tayal

What went wrong with Intel’s 10 nm?

Intel (INTC) finally announced its much-awaited 10 nm (nanometer) product after delaying its release for three years. It started working on the 10 nm node back in 2013.

At that time, it planned to make the 10 nm node 2.7 times denser than the 14 nm node by incorporating new technologies, such as self-aligned quad patterning, contact over active gate processes, cobalt interconnects, and new packaging technologies EMIB (Embedded Multi-Die Interconnect Bridge) and Foveros. The plan was an ambitious one, with the company trying to bring too many technologies onto one node.

INTC Adjusts Technology Road Map to Incorporate Node Optimization

The complexity of the design led to several technical difficulties and yield issues, which delayed the initial release of the 10 nm node from 2016 to 2019. Intel filled the three-year gap by optimizing its 14 nm node and releasing the 14 nm+ and 14 nm++ CPUs (central processing unit), which delivered over 20% performance improvements from its first 14 nm Broadwell CPU.

Intel changes its technology road map

With the changing times, Moore’s law has slowed as technology has become more complex. Moore’s law states that transistor density will double every two years via a node shrink, thereby increasing performance and power efficiency and reducing costs.

Learning from its 14 nm and 10 nm experiences, Intel has adjusted its future product road map. Transistor density will still double with every new node, but each node will also have optimizations. At its Investor Day 2019, Intel revealed its road map, in which the 7 nm node is set to launch in 2021, the 7 nm+ in 2022, and the 7 nm++ in 2023.

Intel will also ease its design rules and keep it simple in order to execute the road map. It will introduce extreme ultraviolet lithography and the Foveros and EMIB packaging technologies in the 7 nm node.

Intel will focus not only on the process node but also on advanced packaging technologies that go beyond single die and integrate individual chips into a heterogeneous device. It will also focus its technology efforts on architecture, memory, interconnectivity, security, and software.

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