A Look at Micron’s Strategy for Scaling NAND Technology



Micron invests in advanced NAND technology

In the NAND (negative AND) market, where demand is sensitive to price, NAND makers have to keep their costs low to sell NAND at a lower price.

Samsung (SSNLF) has been the leader in the 3D NAND space due to its market share and cost leadership. However, Micron Technology (MU) has continued to invest in advanced nodes, and at current it has attained cost leadership.

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Micron’s strategy for scaling NAND technology

At its 2018 Investor Day, Micron’s head of technology development, Scott DeBoer, explained the company’s strategy to scale NAND technology. In 2013, Micron had a significant cost disadvantage over its competitors with its 20 nm (nanometer) MLC (multi-level cell) NAND. Over the years, the company has invested in the advanced node.

The turning point for Micron’s NAND business came in 2015, when in collaboration with Intel (INTC), it transitioned to a 32-layer 3D NAND using CUA (CMOS [complementary metal oxide semiconductor] under array) architecture. It was this architecture that brought Micron significant cost savings.

In 2017, Micron adopted array stacking, a cost-effective way of scaling 3D NAND. It used this technology in combination with CUA architecture to develop the 64-layer 3D NAND, in which it stacked two 32-layer arrays, bringing a 50% increase in layers.

Micron is using the same architecture for the third time in its upcoming 96-layer 3D NAND, which would stack two 48-layer arrays. With this, Micron will end its partnership with Intel and manufacture future generation NANDs by itself.

Fourth-generation 3D NAND

DeBoer stated that in fourth-generation 3D NAND, Micron will use a combination of CUA and charge trap cell technology that will increase bandwidth by over 30% and reduce power consumption by over 40%.

Other than scaling, Micron is also investing in high-value NAND solutions. We’ll look into this next.


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