TSMC’s capacity utilization
In the previous part of the series, we saw that TSMC’s (TSM) gross margin is being impacted by a higher mix of the new 7-nm (nanometer) node and low-margin back-end processing. The gross margin is set to improve as 7-nm matures and the foundry shifts to premium packaging solutions.
Another factor pulling down TSMC’s gross margin is the lower utilization rate of the 28-nm node due to faster-than-expected migration to the 7-nm node. In the third quarter, its 28-nm process utilization rate was below 90% as 28-nm products faced an oversupply situation. It expects oversupply to be a multi-year trend.
On the third quarter earnings call, TSMC’s chief financial officer, Lora Ho, stated that the foundry would use some of its mature nodes to make specialty technologies like CMOS (complementary metal-oxide-semiconductor) imaging sensors and power management chips to improve the utilization rate of mature nodes. Moreover, the company plans to fully depreciate the extra 28-nm capacity. She said that the above transition would improve the utilization rate of 28-nm, thereby improving the foundry’s gross margin in the second half of 2019.
TSMC’s profitability is largely governed by gross margin, while its operating expenses are largely governed by R&D (research and development) surrounding new manufacturing technology nodes. As it invests in the R&D of lower nodes like 7-nm+ and 5-nm, its operating expense increases.
In the third quarter, TSMC increased its revenue by 8.1% sequentially and only increased operating expense by 1.9%, which improved its operating expense ratio to 10.8% from 11.3% in the second quarter. An improved operating efficiency increased its operating margin from 36.2% to 36.6% and net margin from 31.0% to 34.2% during the same period.
Even Intel (INTC) improved its operating efficiency by focusing its R&D efforts on fast-growing segments of high-performance computing. The transition to advanced nodes is increasing TSMC’s capital expenditure. We will look into this next.
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