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Micron’s Plan to Scale Down on DRAM Technology

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Micron’s DRAM technology road map

Micron Technology (MU) is investing in advanced nodes, as they provide the best return on investment opportunity by offering cost competitiveness.

At its 2018 Investor Day, Micron’s head of technology development, Scott DeBoer, talked about the DRAM (dynamic random-access memory) technology road map beyond the 1Y node, which is currently undergoing customer qualification and plans to start volume production by the second half of 2018.

Micron’s DRAM technology road map

DeBoer stated that Micron would continue to go beyond 10 nm (nanometer) to 1Z to 1 alpha to 1 beta and that all these future nodes would help the company improve its cost competitiveness with Samsung (SSNLF) and SK Hynix. However, he did not state the timeframe for the introduction of these future nodes beyond 1Y. He even explained how these nodes would improve cost competitiveness.

 A10b_Semiconductors_MU DRAM process optimisation

Micron’s scaling path through multiple patterning

DeBoer explained that Micron used single patterning to go below 40 nm DRAM because it was cost effective. However, this technique reached its limit at 20 nm, when the company employed double patterning.

Although double patterning was slightly expensive, its relative cost was affordable. This method reached its limit as Micron moved down to the 10 nm/1Y node. At this point, it adopted quad-level patterning, which has a significantly higher cost but is still cost effective compared to EUV (extreme ultraviolet) lithography.

DeBoer believes that Micron can leverage quad-level patterning to 1 beta DRAM nodes. Beyond 1 beta, Micron might consider EUV lithography. It’s trying to delay EUV because it’s not cost effective, and it hits its scaling limit before quadruple patterning.

Along with scaling, Micron is also investing in assembly and test capabilities to deliver high-value DRAM solutions. We’ll look into this next.

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